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\begin{document}

\title{Optimization of Control Quality in Presence of Faults \\ for Distributed Embedded Systems}
%\title{Synthesis and Optimization of Fault-Tolerant Control Applications on Distributed Embedded Systems}


\date{}


\maketitle

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%\vspace*{-3.3cm}
\begin{abstract}
\vspace*{-.1cm} The susceptibility of embedded electronic devices to
faults has increased substantially due to aggressive shrinking of
transistor sizes. In this paper, we propose a design framework for
distributed embedded control systems that ensures reliable execution
and high quality of control even if some computation nodes fail. When
a node fails, the configuration of the underlying distributed system
changes, meaning that appropriate task mappings and schedules must be
used that are customized for the new situation. The number of
possible configurations due to faults is exponential in the number of
nodes in the system. This design space complexity leads to
unaffordable design time. We demonstrate that it is sufficient to
synthesize mappings for a small number of base configurations to
achieve fault-tolerance in any configuration with failed nodes. In
addition to the minimum level of control quality provided by base
configurations, we propose a design-space exploration approach to
generate mappings and optimize control quality for additional
configurations of the underlying distributed platform.

%The problems raised by this design-space
%complexity are very large requirements on design time and the amount
%of memory to store information related to mappings, schedules, and
%control algorithms. 

%Hence, one cannot afford to synthesize all the
%configurations. In this paper, we propose a method to selectively
%synthesize the mapping and schedule for a small number of
%configurations and yet, provide an elegant fault-tolerance mechanism.

% can withstand fault in any processor.
%With the aggressive shrinking of transistor sizes, the rate of faults in embedded electronic devices has increased substantially. In this paper, we propose a framework to synthesize control applications that run safely on distributed embedded systems, even in the presence of faults. When a computational node fails, the configuration of the underlying distributed system changes. To mantain stability and to optimize the control quality on the new configuration, a new mapping and schedule must be used. Unfortunately, the number of such configurations is exponential in the number of processors in the distributed system. Hence, one cannot afford to synthesize the mapping and schedules for all the configurations. In this paper, we propose a method to synthesize the mapping and schedule for such systems, where we selectively synthesize a small number of configurations and yet, provide guarantees on the fault-tolerant capabilities of the system.% can withstand fault in any processor.
\end{abstract}

\vspace{-2mm}
%\category{E2}{Embedded software}{Real-time single processor scheduling}
%\category{E3}{HW/SW co-design}{Specification, modeling, system-level scheduling and partitioning}


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